As a technology specialist at O'Shea Getz, Dr. Demoracski's practice supports patent prosecution and patent litigation. He has expertise in a wide variety of hardware and software technologies, including: ASIC, FPGA, Board and System Design and Verification, ATM, ATE, Computer Systems, Wired and Wireless Networks, Fault Tolerance, Networking Protocols: ATM, IP, TCP, BVR, 802.1X, SONET, and several software and hardware languages.
Dr. Demoracski has over a decade of industry experience including hardware and software development and validation. He has worked in project management, development, and has performed quality testing and verification. He has also served as a consultant for clients including MIT Draper Labs, Intel, Qualcomm, Teradyne, Nortel Networks, Lucent Technologies, and Analog Devices. Prior to consulting, he was employed as a lead semiconductor engineer and test engineer at Teradyne, Inc. in Boston, MA. Dr. Demoracski was also employed at the start-up Equipe Communications in Acton, MA, as a senior hardware simulation engineer.
At Northeastern University, Dr. Demoracski performed significant research in the areas of hardware and software co-design, EDA tools, fault-tolerance, wireless computer networking, nanotechnology, DNA self-assembly, and formal verification. The Title of his doctoral dissertation was Fault-Tolerant Routing for Wireless Multi-hop Networks. He has co-authored ten scientific publications and authored one. He has served for the IEEE as a manuscript reviewer and as local chair to the IEEE International Symposium on Network Computing and Applications.
Publications
- Fault-Tolerant Beacon Vector Routing for Mobile Ad Hoc Networks, IEEE International Parallel and Distributed Processing Symposium, April 2005, Denver, CO
- An Approach to Functional Decomposition Applied to State-Based Designs, IEEE Rapid System Prototyping Workshop, June 2005, Montreal, Canada.
- Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs, International Workshop on Logic Synthesis, June 2005, San Diego, CA
- Design Verification with 0-In Assertions: A Case Study, First Annual Teradyne Technical Conference, June 2005, Boston, MA
- Cluster-Based Load-Balanced Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, IEEE Dependable Systems and Networks Conference, July 2005, Yokohama, Japan.
- Correctness of Fault-Tolerant Cluster-Based Beacon Vector Routing for Ad Hoc Networks, IEEE International Conference on Wireless and Mobile Computing, Networking and Communications, August 2005, Montreal.
- Performance Analysis of Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, ACM/IEEE Intl. Symposium on Modeling, Analysis and Simulation of Wireless and Mobile Systems, October 2005, Montreal.
- Topology Selection for Fault-Tolerant Beacon Vector Routing in Wireless Sensor Networks, IEEE International Conference on Networking and Services, October 2005, French Polynesia, Tahiti.
- Power Consumption Comparison for Regular Wireless Topologies using Fault-Tolerant Beacon Vector Routing, IEEE International Parallel and Distributed Processing Symposium, April 2005, Greece
- Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly, First Annual IEEE Symposium on Nano-Networks, September 2006, Switzerland.
- A Scalable Framework for Defect Isolation of DNA Self-assembled Networks, The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, September 2007, Rome, Italy.
